A ring oscillator is a device that includes an odd number of NOT gates, e.g., inverters, whose output voltage oscillates between logical high and logical low. The NOT gates of a conventional ring oscillator are attached in a circular chain, causing the output voltage of the last NOT gate of the odd number of NOT gates to be fed back as input to the first NOT gate. Because the chain includes an odd number of NOT gates, the logical voltage exiting the last NOT gate is the logical NOT of the input voltage previously entering the first NOT gate. Thus, the output voltage of each NOT gate within the loop oscillates. Since the output voltage of the last NOT gate is asserted to the first NOT gate a finite amount of time after the previous input voltage, each NOT gate oscillates at a predictable frequency.
Controlling ring oscillator frequency may be helpful to test chips for development and quality control, to facilitate power saving during dormant periods of use, to overcome manufacturing process variations, to overcome differences in chip voltage and temperature environments in applications, and/or to provide a uniform clock frequency specification.
One known technique for controlling ring oscillator frequency is to change the number of inverters in the ring. Example digital gates and semiconductor switches to bypass selected inverters of a serial ring oscillator are described for example in U.S. Pat. No. 4,517,532 to Neidorff, U.S. Pat. No. 5,689,213 to Sher, and U.S. Pat. No. 5,815,043 to Chow. Another known technique includes modifying inverter delay time. Inverters comprised of digitally selectable, parallel-connected tri-state gates, whereby the net drive strength and thus the delay of each inverter can be individually controlled, are described in U.S. Pat. No. 4,517,532 to Motoyama.
These known techniques have disadvantages and limitations that prevent widespread employment in embedded CMOS microprocessor systems, which conventionally operate at the highest possible frequency allowed by the cumulative circuit delays in the microprocessor. These known techniques are not well adapted to Electronic Design Automation (EDA) tools. These known techniques do not lend themselves to logic synthesis using standard cell libraries, and physical synthesis with standard-cell-driven layout techniques. Instead, conventional ring oscillators need custom design and layout in each case, increasing cost and practical time to implement. Further, the Motoyama '532 technique requires tri-state logic, which is incompatible with more widely used logic families for digital CMOS circuits, for which EDA tools are more readily available.
Capability to use EDA tools for ring oscillator design and layout is desirable in current semiconductor technologies for embedded CMOS microprocessor systems, which employ small line widths, e.g., 130 nm and 45 nm, where the wiring delay between stages becomes significant and can exceed the inverter gate delay due to parasitic capacitance. Further, it is desirable to ensure that frequency transitions of a ring oscillator occur without any short pulses, known as runt or splinter pulses, that can cause metastability. Bistable elements can hover between logical high and logical low for extended periods of time, interrupting or stopping normal system operation. A clock oscillator free of metastability is important for embedded microprocessor systems, since for example malfunction in real-time control systems can have serious consequences.
A multi-speed ring oscillator having a physical layout adapted for development using EDA tools, and having frequency transitions without runt pulses would therefore be desirable.